1. Field of the Invention
The invention relates to a semiconductor device manufacturing method, particularly to a packaging technology of a semiconductor device having fine electrodes.
2. Description of the Related Art
Conventionally, a flip chip packaging technology includes a packaging method, in which resin-sealing of a semiconductor chip and electrically connecting of the semiconductor chip and a substrate are simultaneously performed.
FIGS. 3A and 3B are cross-sectional views for describing such a packaging method. As shown in FIG. 3A, a substrate 2 is mounted on a stage 1. A first electrode 3 made of conductive wiring path is formed on a front surface of the substrate 2. Epoxy sealing resin 4 is coated on a region of the substrate 2 where the first electrode 3 is not formed. The sealing resin 4 contains filler 5. The filler 5 is made of silicon particles or metal particles, and mixed in the sealing resin 4 in order to reduce the difference in a coefficient of thermal expansion between the sealing resin 4 and the substrate 2 and between the sealing resin 4 and a semiconductor chip 6, and to lower thermal stress generated by these differences in the coefficient of thermal expansion.
The semiconductor chip 6 is disposed above the substrate 2. A second electrode 7 made of protruding electrodes such as Au bumps is formed on a front surface of the semiconductor chip 6. A movable plate 8, which is configured to move vertically, is attached on a back surface of the semiconductor chip 6.
As shown in FIG. 3B, with the first electrode 3 and the second electrode 7 being aligned, the movable plate 8 is lowered in a direction shown by an arrow in FIG. 3B, to apply load to and press the whole surface of the semiconductor chip 6. Then, the sealing resin 4 is pressed to fill the space between the substrate 2 and the semiconductor chip 6, and the second electrode 7 is pressed against the first electrode 3 (that is, the electrodes 3 and 7 are mechanically attached and electrically connected with each other.) Thus, the resin-sealing of the semiconductor chip 6 and the electrically connecting of the semiconductor chip 6 and the substrate 2 have been simultaneously performed. This technology is disclosed in the Japanese Patent Application Publication No. 2000-236002.
However, when the first electrode 3 and the second electrode 7 are pressed into contact with each other by the above method, the sealing resin 4 spreads in a lateral direction. Therefore, the sealing resin 4 itself or the filler 5 contained in the sealing resin 4 are interposed between the first electrode 3 and the second electrode 7. This causes poor electric connection between the first electrode 3 and the second electrode 7.